A number of devices, for instance mobile applications such as portable devices, require the use of a frequency synthesizer for operation. One such frequency synthesizer includes a digital-to-phase converter having a digital delay-locked loop (DLL). FIG. 1 illustrates a schematic diagram of a prior art DLL 10 configuration for generating an output signal 72 at a desired frequency Fout. DLL 10 comprises a fixed frequency synthesizer 20 for generating a clock signal 22 having a frequency of Fclk. DLL 10 further comprises: a delay line 30 having N number of adjustable delay elements D1 through DN; a phase detector 40, a charge pump 50 and a loop filter 60, which make up a stabilization circuit for DLL 10; a selection circuit 70 that may be, for instance, a multiplexer (also referred to herein as a “MUX”); and a digital control device 90.
In operation, delay line 30 receives the clock signal 22 into an input and then generates a set of time delayed clock signals at a plurality of outputs. The time delays are generated by delay elements D1 through DN, which are connected in cascade and which may be, for instance, inverter gates, transmission line gates, and the like, depending upon a desired DLL implementation. Moreover, an overall time delay between a signal at first point on the delay line, which is typically an input of the first delay element D1, and a signal at a second point on the delay line, which is typically the output of the Nth delay element DN, is controlled by a bias voltage Vtune input into delay line 30. This overall delay may be, for instance, a wavelength (i.e., 360 degrees) which is 1 period of clock signal 22, a half wavelength (i.e., 180 degrees) which is ½ period of clock signal 22, or whatever delay is required for a particular application. Ideally, each delay element will replicate the input waveform, with a time delay, at the delay element output that is equal to the total delay from the input of delay element D1 through the output of delay element DN divided by the total number of delay elements (i.e., N).
Each delay element D1–DN has an output tap T1–TN, respectively, which is connected to an input of MUX 70. In addition, a tap T0 is connected between the input of the delay element D1 and an input of MUX 70 in order to supply the clock signal 22 thereto. Each delay element D1–DN delays the propagation of the clock signal 22 and outputs on its corresponding output tap T1–TN, respectively, a corresponding phase shifted clock signal. Accordingly, the number N of phase-shifted clock signals output by delay elements D1–DN are supplied via output taps T1–TN to the inputs of MUX 70 along with the clock signal 22 output on tap T0.
To ensure stability during operation, DLL 10 includes phase detector 40 that is typically connected to receive the clock signal 22 from synthesizer 20 and a phase shifted clock signal from delay line 30, which in this instance is the signal at the output of delay element DN. Phase detector 40 compares the phase difference between the clock signal 22 and the phase shifted clock signal to a predetermined desired phase shift and outputs to the charge pump an error signal that is a function of the result of this comparison. Those of ordinary skill in the art should realize that phase detector 40 could be configured for comparing the phase difference between the signals at any two points on the delay line to the predetermined desired phase shift and outputting the corresponding error signal.
The charge pump 50 deposits a corresponding charge on the loop filter 60, which in turn converts the error signal into a DLL tuning signal which is supplied to delay line 30 to adjust the bias voltage Vtune in a manner that maintains the phase relationship between the phase shifted clock signal and the clock signal 22 during operation of DLL 10, i.e., until the total delay through the delay line is the desired delay. Once DLL 10 has stabilized, MUX 70 operates in a conventional way under the control of digital control 90 to connect, one at a time, a sequence of phase-shifted clock signals at taps T0–TN to corresponding outputs of MUX 70 to provide an output signal at the desired output frequency Fout. The digital control device 90 is typically a tap selection controller that comprises two accumulators, one to determine when to connect a tap to an output terminal and another to determine which tap to connect. This tap selection sequence is typically based on Fout, Fclk and N.
There are a finite number of transitions that can be selected from the delay line 30 to create an output signal at a desired frequency. The possible error associated with the selection of a given tap to create the output signal causes a quantization effect which creates spurious signal outputs (spurious being undesired spectral components). The effect can be minimal if the selected frequency and the clock signal frequency happen to fall on certain values. However, in general the spurious free dynamic range will be limited by the quantization effect of the taps.
FIG. 2 illustrates the misalignment between the desired output signal transitions and those of the actual output signal 72 generated in DLL 10. This misalignment is caused by a round off error which results in spurious signals generated at the output 72 of MUX 70. Let us assume that delay line 30 includes four delay elements D1 through D4. FIG. 2, accordingly, illustrates clock signal 22 (i.e. waveform 210 having no time delay or a zero phase shift) and three corresponding time delayed or phase-shifted clock signals (i.e., waveforms 220, 230 and 240) output therefrom. Assuming a total delay from the input of D1 to the output of D4 is one wavelength, the waveform output from D4 would be equivalent to waveform 210. As FIG. 2 illustrates, each waveform ideally has the same frequency as the clock signal 22 (i.e., Fclk) but may have a different delay in time. Moreover, in this illustration from a time t0 to a time t4, twenty-two edge transition times or delay times (i.e., d0 through d21) are generated from which MUX 70 can select to generate the desired output waveform 260.
Given the number of taps, the frequency of the clock signal 22, and the desired output frequency, the potential delay times can be calculated by digital control device 90 and selected by MUX 70 to generate a corresponding output signal 250. This relationship may, for instance, be represented by the following equation:Fclk=(M*Fout)/N, for M≧N  (1)where Fclk is the frequency of the clock signal 22, Fout is the desired output frequency, N is the number of taps and M represents the delays that would be required to generate the desired output signal waveform 260. This relationship may, alternatively, be represented by the following equation:Tout=(M*Tclk)/N, for M≧N  (2)where M and N are the same as in equation (1), Tclk is the period of Fclk, Tout is the period of Fout and Tclk/N represents a delay caused by a single delay element. Ideally, to generate an output signal having no spurious signals, M would equal an integer number of delays (i.e., delays=Tclk/N). However, typically this is not the case. Generally, M is a non-integer multiple of delays and taps are then selected above and below the desired multiple of delays thereby generating a waveform 250 that has the desired output period on average.
Referring again to FIG. 2, assume that M=5.4, for example, for a given Tout, Tclk and N. In this case, the edge transition times for the desired output waveform 260 would be at 5.4 delays, 10.8 delays, 16.2 delays, 21.6 delays, etc. To generate the closest waveform 250 to the desired waveform 260, the desired delays would be rounded to the nearest integer multiple of delays, e.g., 5 delays (d5), 11 delays (d11), 16 delays (d16), 22 delays (d22), etc. This round-off error or quantization effect causes the spurious outputs. Thus, the farther the actual selected delay is from the desired delay (i.e., the larger the round-off error) the larger the corresponding spurious signal being generated at the output.
One way known in the art of improving the spurious performance or reducing the spurious level relative to the desired output signal is to increase the number of taps in the delay line 30. This would result in the actual selected delays being closer to the desired delays (i.e., smaller round-off errors) and resulting smaller spurious signals being generated at the output. However, a limitation of this solution is that each tap that is added degrades the noise performance of the DLL and increases the complexity of the tap selection circuitry 70. In addition, although theoretically an infinite number of taps may be added, practically the number of taps possible is limited as present day technologies will not support the complex level of circuitry needed if the number of taps increases beyond a certain point, e.g., where the tap selection network switching delay approaches a 10% fraction of Tclk.
Another method known in the art for improving the spurious performance is the use of dither. However, in general, while the use of dither reduces the spurious energy at specific frequencies, it also essentially spreads this energy over a broader bandwidth thereby creating a floor of quantization noise. Thus, to decrease the spurious signal, and accordingly this wide band noise, to an acceptable level in certain applications, an unrealizable number of taps in addition to the dither would be required.
Thus, there exists a need for a DLL configuration that minimizes the level of spurious signals without requiring more taps to be added to the DLL and that further does not require the use of dither with its associated wide band noise.